1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device in which a separation (isolation) diffusion layer separates a plurality of device formation regions from one another.
2. Background Art
FIG. 7 is a plan view showing the structure of a conventional semiconductor device. FIG. 8 is a schematic cross-sectional view of the semiconductor taken along chain line II-IIxe2x80x2 device of FIG. 7. This semiconductor device is used as, for example, a driver for automobiles, motors, etc. FIG. 8 shows a state in which devices in an epitaxial layer (hereinafter referred to as an epi layer) on a P type silicon substrate 101 are separated from one another. FIG. 9 is also a schematic cross-sectional view of the semiconductor device obtained as a result of additionally forming aluminum wires 106 in the example of FIG. 8.
As shown in FIG. 8, a P+ diffusion layer 103, which constitutes a separation diffusion layer, divides the Nxe2x88x92 epi layer formed on a P type silicon substrate 101 into an Nxe2x88x92 epi layer 102 and Nxe2x88x92 epi layers 104. The Nxe2x88x92 epi layer 102 constitutes an area adjacent to the dicing area around the chip and is hereinafter referred to as an invalid area, while the Nxe2x88x92 epi layers 104 each constitute a device formation region. A device separation oxide film 105 is formed on each predetermined area on the Nxe2x88x92 epi layer 102 and the P+ diffusion layer 103 by the use of the so-called LOCOS method.
FIG. 10 is a schematic cross-sectional view showing a MOS transistor and an NPN bipolar transistor formed in Nxe2x88x92 epi layers 104 in detail.
As shown in FIG. 10, a DMOS (Double Diffusion MOS) device 112 is formed of Pxe2x88x92 diffusion layers 107 (backgate regions), N+ diffusion layers 108 (source/drain regions), a gate oxide film 110, and a gate wire 111 in an Nxe2x88x92 epi layer 104.
On the other hand, an NPN bipolar transistor 113 is formed of an N+ diffusion layer 121, a P diffusion layer 122, an N diffusion layer 123, and an N+ diffusion layer 124 in another Nxe2x88x92 epi layer 104 (device formation region) separated by the P+ diffusion 103, which constitutes an active area. The N+ diffusion layer 121 and the P diffusion layer 122 constitute the emitter region and the base region, respectively, whereas the N diffusion layer 123 and the N+ diffusion layer 124 collectively constitute the collector region.
Further, as shown in FIG. 9, the aluminum wires 106 are formed on both the Nxe2x88x92 epi layer 102 (invalid area) and the P+ diffusion layer 103 adjacent to the invalid area. The aluminum wires 106 are each used to apply a predetermined voltage to the P+ diffusion layer 103 or Nxe2x88x92 epi layer 102. To do this, the aluminum wires 106 on the P+ diffusion layer 103 are formed separately and independently of the aluminum wires 106 on the Nxe2x88x92 epi layer 102.
However, when a load having an inductance component L (hereinafter referred to as an L load), such as a motor, was connected to a semiconductor device formed in a device formation region in the above conventional structure, a problem arose that device malfunction occurred due to a counterelectromotive force generated by the L load.
FIG. 11 is a schematic diagram showing a portion of an output circuit used in drivers for automobiles, motors, etc. It should be noted that N channel MOS transistors 125 and 126 are formed in device formation regions on the P type silicon substrate 101, and collectively constitute a driver output circuit. The drain of the N channel MOS transistor 125 and the source of the N channel MOS transistor 126 are connected to an L load (namely a coil 127 in the figure) such as a motor. Further, the source of the N channel MOS transistor 125 is grounded, while a positive potential Vcc is applied to the drain of the N channel MOS transistor 126.
A description will be made of the counterelectromotive force produced by the L load with reference to FIG. 11. First, the N channel MOS transistor 126 is turned on to cause a current to flow in the coil 127, producing an induced magnetic field in the coil 127. Then, if the N channel MOS transistor 126 is turned off, the N channel MOS transistor 125 is supplied with electrons by an induced current generated by the magnetic field in the coil 127. The above phenomenon in which an induced current flows after turning off the N channel MOS transistor 126 is called xe2x80x98a counterelectromotive force by an L loadxe2x80x99.
FIG. 12 includes both a schematic cross-sectional view (similar to that of FIG. 9) of the semiconductor device taken along chain line I-Ixe2x80x2 of FIG. 2 and a schematic diagram for illustrating a problem with the conventional structure. As shown in FIG. 12, in the conventional semiconductor device structure, a parasitic NPN transistor 114 is unintentionally formed such that its emitter is an Nxe2x88x92 epi layer 104 (device formation region), its base is the P type silicon substrate 101 and P+ diffusion layer 103, and its collector is the Nxe2x88x92 epi layer 102 (invalid area).
In addition, a parasitic NPN transistor 115 is unintentionally formed such that its emitter is the Nxe2x88x92 epi layer 102 (invalid area), and its base is the P type silicon substrate 101 and the P+ diffusion layer 103, and its collector is an Nxe2x88x92 epi layer 104 (device formation region). Thus, both the collector of the parasitic NPN transistor 114 and the emitter of the parasitic NPN transistor 115 are formed of the Nxe2x88x92 epi layer 102 (invalid area), which is formed in a rectangular ring along the dicing area as shown in FIG. 7. Therefore, the collector of the parasitic NPN transistor 114 and the emitter of the parasitic NPN transistor 115 are electrically connected to each other.
First, a description will be made of what causes the malfunction when an L load is connected in the conventional structure. If an L load is connected to a device such as a MOS transistor or an NPN bipolar transistor formed in an Nxe2x88x92 epi layer 104, electrons flow from the Nxe2x88x92 epi layer 104 (device formation region) to the P type silicon substrate 101 due to a counterelectromotive force generated by the L load. This activates the parasitic NPN transistor 114 which in turn supplies electrons to the Nxe2x88x92 epi 102 layer (invalid area).
Since aluminum wires 106 are formed on the Nxe2x88x92 epi layer 102 (invalid area), the resistance component 120 of the Nxe2x88x92 epi layer 102 is low. Therefore, the epi layer 102 (invalid area) supplied with the electrons acts as the emitter of the parasitic NPN transistor 115.
Generally, the P type silicon substrate 101 is connected to GND (grounded) such that its potential is 0 V. However, it is difficult to set all the areas (portions) to 0 V, producing a potential difference on the order of 10xe2x88x921 V at some places. Then, if the potential of the P type silicon substrate 101 (which acts as the base of the parasitic NPN transistor 115) varies, the parasitic NPN transistor 115 operates, and as a result electrons flow into another device formation region in the active area. This phenomenon has caused the problem that malfunction of a device occurs in the device formation region into which the electrons have flown.
In view of the foregoing, the present invention has been made, and an object of the present invention is to provide a semiconductor device capable of preventing occurrence of malfunction caused by a counterelectromotive force produced by an L load.
According to one aspect of the present invention, a semiconductor device comprises a semiconductor layer formed on a semiconductor substrate, a separation diffusion layer, and a conductive film. The separation diffusion layer divides the semiconductor layer into a device formation area, which is an active area, and an invalid area outside the active area. The conductive film is for electrically connecting the invalid area of the semiconductor layer to the separation diffusion layer.
Since a semiconductor layer constituting an invalid area is electrically connected to a separation diffusion layer, the potential of the invalid area can be made equal to that of the separation diffusion layer. Therefore, even when electrons are supplied to a device formation region by a counterelectromotive force produced by an L load connected to a device formation region, it is possible to prevent electron supply from the separation diffusion layer to the invalid area, thereby preventing device malfunction.
Other and further objects, features and advantages of the invention will appear more fully from the following description.